Placing ferroelectric material between the plates of a capacitor on a semiconductor substrate causes the capacitor to exhibit a memory effect in the form of charge polarization between the plates of the capacitor. In effect, when the capacitor is charged with the field lines running in one direction across the capacitor plates, a residual charge polarization remains after the charge is removed from the capacitor plates. If an opposite charge is placed on the capacitor plates, an opposite residual polarization remains. A plot of the applied field voltage (E) across the plates of the capacitor against the polarization (P) of the ferroelectric material between the plates of the capacitor exhibits a classic hysteresis curve as shown in FIG. 1. This type of hysteresis response of ferroelectric material between the plates of the capacitor manufactured on a semiconductor die as known in the art and is described in U.S. Pat. No. 4,873,664 to Eaton Jr., which is incorporated herein by reference.
Using ferroelectric material in the manufacture of capacitors for use in the cells of memory arrays is also known in the art. By applying a coercive voltage across the plates of the ferroelectric capacitor to produce one polarization or another, the residual polarization stores a nonvolatile 1 or 0 in the cell. If a ferroelectric capacitor has zero volts applied across its plates, it may be polarized as indicated by either point A or point D in FIG. 1. Assuming that the polarization is at point A, if a positive voltage is applied across the capacitor which is greater than the "coercive voltage" indicated by line B, then the capacitor will conduct current and move to a new polarization at point C. When the voltage across the capacitor returns to zero, the polarization will remain the same and move to point D. If a positive voltage is applied across the capacitor when it is polarized at point D, the capacitor will not conduct current, but will move to point C. It can be seen that a negative potential can be used to change the polarization of a capacitor from point D to point A. Therefore, points A and D can represent two logic states occurring when zero volts are applied to the capacitor and which depend upon the history of voltage applied to the capacitor.
The reading of the polarization of the ferroelectric capacitor can be a destructive read in which a pulse is applied to the ferroelectric capacitor and the amount of resultant charge is either low if the pulse polarity agreed with the previous memorization polarity, or the resultant charge is higher if the charge polarity placed on the capacitor is of the opposite polarity last placed across the plates of the capacitor. This minute difference between an agreeable charge and an opposite charge can be measured to determine what the previous polarization on the ferroelectric capacitor was as it was last written. If a large charge results from reading a memory cell, the memory cell polarization will move from one state to the other state, for example point A to Point D. Thus, the data read from the memory cell must be restored.
The fact that the ferroelectric capacitors require a destructive read to determine the last polarization, and the fact that the resultant charge differences of the ferroelectric capacitor between an agreeable applied pulse and an opposite applied pulse make the technique of reading and writing ferroelectric memories a difficult task. The benefit of having a nonvolatile memory in which stored data remains without any battery backup or other external application of power is of great use in the computer and control industries. However, for any such nonvolatile memories to be of any use, the memories must be of a high enough density and must have a fast enough response time to make them commercially more attractive than battery backed up DRAM, mechanical disk storage and other types of nonvolatile storage.
Ferroelectric memories traditionally do not have high operating speeds comparable to that of DRAM storage devices. Referring to FIG. 2, each memory storage cell comprises a pair of ferroelectric capacitors and a pair of access transistor. One plate of the pair of ferroelectric capacitors is connected to a plate line, while the other plates of the ferroelectric capacitor are connected through access transistors to separate bit lines. In operation, a momentary voltage pulse is placed on the ferroelectric capacitors between the bit lines and the plate line to polarize the ferroelectric material of the two ferroelectric capacitors, resulting in a polarization of one direction for one capacitor and an opposite polarization for the second ferroelectric capacitor. This concept can be taken a step further by using a regular array of ferroelectric capacitors, whereby each cell contains two ferroelectric capacitors and two access transistors. The ferroelectric capacitors within each memory cell receive complementary input signals such that the ferroelectric capacitors are polarized in opposite states to indicate a 1 or a 0. When the pairs of capacitors for each cell are read, a resulting voltage on the bit lines, which result from applying a pulse on a plate line, is compared using a differential sense amplifier to compare the voltages on the bit lines and thus determine the polarity on the ferroelectric capacitors within the cell. The disadvantage of the above approach is that it requires that each cell contain at least two transistors and two ferroelectric capacitors. This approach takes up a large area of the chip for implementation, which limits the overall density of a memory array.
Ferroelectric memories have an array of memory cells which can be arranged in rows and columns where a row of cells share a common plate line. A memory array typically has a plate line which is associated with a row of memory. The plate line is a single conductor which is driven by a single driver circuit. Alternately, a memory can include a divided plate line. The plate line for a row of the array in this architecture is separated into different sections which are driven by a single driver circuit. See 1194 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, "A 256 kb Nonvolatile Ferroelectric Memory at 3 V and 100 ns" by Tatsumi Sumi, February 1994 for a description of a divided plate line memory device, incorporated herein by reference. See also U.S. Pat. No. 5,638,256, and U.S. patent application Ser. No. 08/520,257 for descriptions of a ferroelectric memory device, incorporated herein by reference.
Still lacking in the industry is a ferroelectric capacitor cell memory array using a RAM architecture which provides a fast efficient cell plate operation and structure. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a ferroelectric memory which has segmented plate lines and a plurality of plate line drivers.